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MPC603E7VEC/d (motorola order number) 11/96 rev 1 g522-0267-00 (ibm order number) the powerpc name, the powerpc logotype, powerpc 603, and powerpc 603e are trademarks of international business machines corporation, used by motorola under license from international business machines corporation. this document contains information on a new product under development by motorola and ibm. motorola and ibm reserve the right to motorola inc., 1996. all rights reserved portions hereof international business machines corporation, 1991?996. all rights reserved pid7v-603e hardware speci?ations change or discontinue this product without notice. advance information powerpc 603e risc microprocessor family: pid7v-603e hardware speci?ations the powerpc 603e microprocessor is an implementation of the powerpc family of reduced instruction set computing (risc) microprocessors. in this document, the term ?03e is used as an abbreviation for ?owerpc 603e microprocessor? the powerpc 603e microprocessors are available from motorola as mpc603e and from ibm as ppc603e. note that the 603e is implemented in both a 2.5-volt version (pid 0007v powerpc 603e microprocessor, abbreviated as pid7v-603e) and a 3.3-volt version (pid 0006 powerpc 603e microprocessor, abbreviated as pid6-603e). this document describes the pertinent physical characteristics of the pid7v-603e. for functional characteristics of the processor, refer to the powerpc 603e risc microprocessor users manual . this document contains the following topics: topic page section 1.1, ?verview 2 section 1.2, ?eatures 3 section 1.3, ?eneral parameters 4 section 1.4, ?lectrical and thermal characteristics 4 section 1.5, ?owerpc 603e microprocessor pin assignments 17 section 1.6, ?owerpc 603e microprocessor pinout listings 19 section 1.7, ?owerpc 603e microprocessor package descriptions 23 section 1.8, ?ystem design information 29 section 1.9, ?rdering information 37 appendix a, ?eneral handling recommendations for the c4-cqfp package 38
2 pid7v-603e hardware specifications preliminary?ubject to change without notice to locate any published errata or updates for this document, refer to the website at http://www.mot.com/ powerpc/ or at http://www.chips.ibm.com/products/ppc. 1.1 overview this section describes the features of the 603e and describes brie? how those units interact. the 603e is a low-power implementation of the powerpc microprocessor family of reduced instruction set computing (risc) microprocessors. the 603e implements the 32-bit portion of the powerpc architecture speci?ation, which provides 32-bit effective addresses, integer data types of 8, 16, and 32 bits, and ?ating- point data types of 32 and 64 bits. for 64-bit powerpc microprocessors, the powerpc architecture provides 64-bit integer data types, 64-bit addressing, and other features required to complete the 64-bit architecture. the 603e provides four software controllable power-saving modes. three of the modes (the nap, doze, and sleep modes) are static in nature, and progressively reduce the amount of power dissipated by the processor. the fourth is a dynamic power management mode that causes the functional units in the 603e to automatically enter a low-power mode when the functional units are idle without affecting operational performance, software execution, or any external hardware. the 603e is a superscalar processor capable of issuing and retiring as many as three instructions per clock. instructions can execute out of order for increased performance; however, the 603e makes completion appear sequential. the 603e integrates ?e execution units?n integer unit (iu), a ?ating-point unit (fpu), a branch processing unit (bpu), a load/store unit (lsu), and a system register unit (sru). the ability to execute ?e instructions in parallel and the use of simple instructions with rapid execution times yield high ef?iency and throughput for 603e-based systems. most integer instructions execute in one clock cycle. the fpu is pipelined so a single-precision multiply-add instruction can be issued every clock cycle. the 603e provides independent on-chip, 16-kbyte, four-way set-associative, physically addressed caches for instructions and data and on-chip instruction and data memory management units (mmus). the mmus contain 64-entry, two-way set-associative, data and instruction translation lookaside buffers (dtlb and itlb) that provide support for demand-paged virtual memory address translation and variable-sized block translation. the tlbs and caches use a least-recently used (lru) replacement algorithm. the 603e also supports block address translation through the use of two independent instruction and data block address translation (ibat and dbat) arrays of four entries each. effective addresses are compared simultaneously with all four entries in the bat array during block translation. in accordance with the powerpc architecture, if an effective address hits in both the tlb and bat array, the bat translation takes priority. the 603e has a selectable 32- or 64-bit data bus and a 32-bit address bus. the 603e interface protocol allows multiple masters to compete for system resources through a central external arbiter. the 603e provides a three-state coherency protocol that supports the exclusive, modi?d, and invalid cache states. this protocol is a compatible subset of the mesi (modi?d/exclusive/shared/invalid) four-state protocol and operates coherently in systems that contain four-state caches. the 603e supports single-beat and burst data transfers for memory accesses, and supports memory-mapped i/o. the 603e uses an advanced, 2.5/3.3-v cmos process technology and maintains full interface compatibility with ttl devices.
pid7v-603e hardware specifications 3 preliminary?ubject to change without notice 1.2 features this section summarizes features of the 603es implementation of the powerpc architecture. major features of the 603e are as follows: high-performance, superscalar microprocessor as many as three instructions issued and retired per clock as many as ?e instructions in execution per clock single-cycle execution for most instructions pipelined fpu for all single-precision and most double-precision operations five independent execution units and two register ?es bpu featuring static branch prediction a 32-bit iu fully ieee 754-compliant fpu for both single- and double-precision operations lsu for data transfer between data cache and gprs and fprs sru that executes condition register (cr), special-purpose register (spr) instructions, and integer add/compare instructions thirty-two gprs for integer operands thirty-two fprs for single- or double-precision operands high instruction and data throughput zero-cycle branch capability (branch folding) programmable static branch prediction on unresolved conditional branches instruction fetch unit capable of fetching two instructions per clock from the instruction cache a six-entry instruction queue that provides lookahead capability independent pipelines with feed-forwarding that reduces data dependencies in hardware 16-kbyte data cache?our-way set-associative, physically addressed; lru replacement algorithm 16-kbyte instruction cache?our-way set-associative, physically addressed; lru replacement algorithm cache write-back or write-through operation programmable on a per page or per block basis bpu that performs cr lookahead operations address translation facilities for 4-kbyte page size, variable block size, and 256-mbyte segment size a 64-entry, two-way set-associative itlb a 64-entry, two-way set-associative dtlb four-entry data and instruction bat arrays providing 128-kbyte to 256-mbyte blocks software table search operations and updates supported through fast trap mechanism 52-bit virtual address; 32-bit physical address facilities for enhanced system performance a 32- or 64-bit split-transaction external data bus with burst transfers support for one-level address pipelining and out-of-order bus transactions
4 pid7v-603e hardware specifications preliminary?ubject to change without notice integrated power management low-power 2.5/3.3-volt design internal processor/bus clock multiplier that provides 2/1, 2.5/1, 3/1, 3.5/1, 4/1, 4.5/1, 5/1, 5.5/1, and 6/1 ratios three power saving modes: doze, nap, and sleep automatic dynamic power reduction when internal functional units are idle in-system testability and debugging features through jtag boundary-scan capability 1.3 general parameters the following list provides a summary of the general parameters of the pid7v-603e: technology 0.35 m m cmos, ?e-layer metal die size 10.5 mm x 7.5 mm (79 mm 2 ) transistor count 2.6 million logic design fully-static package surface mount 240-pin ceramic quad ?t pack (cqfp) or 255 ceramic ball grid array (bga) core power supply 2.5 5% v dc i/o power supply 3.3 5% v dc 1.4 electrical and thermal characteristics this section provides the ac and dc electrical speci?ations and thermal characteristics for the pid7v- 603e. 1.4.1 dc electrical characteristics the tables in this section describe the pid7v-603e dc electrical characteristics. table 1 provides the absolute maximum ratings.
pid7v-603e hardware specifications 5 preliminary?ubject to change without notice table 2 provides the recommended operating conditions for the pid7v-603e. table 3 provides the package thermal characteristics for the pid7v-603e. table 1. absolute maximum ratings characteristic symbol value unit core supply voltage vdd ?.3 to 2.75 v pll supply voltage avdd ?.3 to 2.75 v i/o supply voltage ovdd ?.3 to 3.6 v input voltage v in ?.3 to 5.5 v storage temperature range t stg ?5 to 150 c notes : 1. functional and tested operating conditions are given in table 2. absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. stresses beyond those listed may affect device reliability or cause permanent damage to the device. 2. caution : v in must not exceed ovdd by more than 2.5 v at any time, including during power-on reset. 3. caution : ovdd must not exceed vdd/avdd by more than 1.2 v at any time, including during power-on reset. 4. caution : vdd/avdd must not exceed ovdd by more than 0.4 v at any time, including during power-on reset. table 2. recommended operating conditions characteristic symbol value unit core supply voltage vdd 2.375 to 2.625 v pll supply voltage avdd 2.375 to 2.625 v i/o supply voltage ovdd 3.135 to 3.465 v input voltage v in gnd to 5.5 v junction temperature tj 0 to 105 c note: these are the recommended and tested operating conditions. proper device operation outside of these conditions is not guaranteed. table 3. thermal characteristics characteristic symbol value rating motorola wire-bond cqfp package thermal resistance, junction-to-case (typical) q jc 2.2 c/w ibm c4-cqfp package thermal resistance, junction-to-case q jc 3.6 c/w bga package thermal resistance, junction-to-top-of-die q jc 0.03 c/w note: refer to section 1.8, ?ystem design information, for more details about thermal management.
6 pid7v-603e hardware specifications preliminary?ubject to change without notice table 4 provides the dc electrical characteristics for the pid7v-603e. table 4. dc electrical specifications vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5% v dc, gnd = 0 v dc, 0 tj 105 c characteristic symbol min max unit notes input high voltage (all inputs except sysclk) v ih 2.0 5.5 v input low voltage (all inputs except sysclk) v il gnd 0.8 v sysclk input high voltage cv ih 2.4 5.5 v sysclk input low voltage cv il gnd 0.4 v input leakage current, v in = 3.465 v i in ?0 m a 1,2 v in = 5.5 v i in 300 m a 1,2 hi-z (off-state) leakage current, v in = 3.465 v i tsi ?0 m a 1,2 v in = 5.5 v i tsi 300 m a 1,2 output high voltage, i oh = ? ma v oh 2.4 v output low voltage, i ol = 7 ma v ol 0.4 v capacitance, v in = 0 v, f = 1 mhz (excludes ts , abb , dbb , and ar tr y ) c in 10.0 pf 3 capacitance, v in = 0 v, f = 1 mhz (for ts , abb , dbb , and ar tr y ) c in 15.0 pf 3 notes : 1. excludes test signals (lssd_mode, l1_tstclk, l2_tstclk, and jtag signals). 2. the leakage is measured for nominal ovdd and vdd or both ovdd and vdd must vary in the same direction (for example, both ovdd and vdd vary by either +5% or -5%). 3. capacitance is periodically sampled rather than 100% tested.
pid7v-603e hardware specifications 7 preliminary?ubject to change without notice table 5 provides the power consumption for the pid7v-603e. 1.4.2 ac electrical characteristics this section provides the ac electrical characteristics for the pid7v-603e. these speci?ations are for 160, 166, 180, 200, 225, 233, and 240 mhz processor core frequencies. the processor core frequency is determined by the bus (sysclk) frequency and the settings of the pll_cfg[0?] signals. all timings are speci?d respective to the rising edge of sysclk. pll_cfg signals should be set prior to power up and not altered afterwards. 1.4.2.1 clock ac speci?ations table 6 provides the clock ac timing speci?ations as de?ed in figure 1. after fabrication, parts are sorted by maxium processor core frequency as shown in section 1.4.2.1, ?lock ac speci?ations?and tested for conformance to the ac speci?ations for that frequency. parts are sold by maximum processor core frequency; see section 1.9, ?rdering information. table 5. power consumption processor (cpu) frequency unit 160 mhz 166 mhz 180 mhz 200 mhz 220, 225 mhz 233, 240 mhz full-on mode (dpm enabled) typical 2.9 3.0 3.5 4.0 4.4 4.8 w maximum 3.8 4.0 4.5 5.0 5.5 6.0 w doze mode typical 1.2 1.2 1.4 1.5 1.7 1.8 w nap mode typical 75 80 100 120 132 140 mw sleep mode typical 65 70 80 100 110 120 mw sleep mode?ll disabled typical 60 60 60 60 60 60 mw sleep mode?ll and sysclk disabled maximum 60 60 60 60 60 60 mw notes : 1.these values apply for all valid pll_cfg[0?] settings and do not include output driver power (ovdd) or analog supply power (avdd). ovdd power is system dependent but is typically 10% of vdd. worst-case avdd = 15 mw. 2. typical power is an average value measured at vdd = avdd = 2.5 v, ovdd = 3.3v, in a system executing typical applications and benchmark sequences. 3. maximum power is measured at 2.625 v using a worst-case instruction mix.
8 pid7v-603e hardware specifications preliminary?ubject to change without notice table 6. clock ac timing specifications vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5% v dc, gnd = 0 v dc , 0 tj 105 c num characteristic 160 mhz 166 mhz 180 mhz 200 mhz 220, 225 mhz 233, 240 mhz unit notes min max min max min max min max min max min max processor frequency 125 160 125 167 125 180 125 200 125 220, 225 125 233, 240 mhz 1 vco frequency 250 320 250 333 250 360 250 400 250 440, 450 250 466, 480 mhz 1 sysclk frequency 25 66.67 25 66.67 25 66.67 25 66.67 25 75 25 75 mhz 1 1 sysclk cycle time 15 40.0 15 40.0 15 40.0 15 40.0 13.3 40.0 13.3 40.0 ns 2,3 sysclk rise and fall time 2.0 2.0 2.0 2.0 2.0 2.0 ns 2 4 sysclk duty cycle measured at 1.4 v 40.0 60.0 40.0 60.0 40.0 60.0 40.0 60.0 40.0 60.0 40.0 60.0 % 3 sysclk jitter 150 150 150 150 150 150 ps 4 603e internal pll-relock time 100 100 100 100 100 100 m s 3,5 notes : 1. caution : the sysclk frequency and pll_cfg[0?] settings must be chosen such that the resulting sysclk (bus) frequency, cpu (core) frequency, and pll (vco) frequency do not exceed their respective maximum or minimum operating frequencies. refer to the pll_cfg[0?] signal description in section 1.8, ?ystem design information, for valid pll_cfg[0?] settings. 2. rise and fall times for the sysclk input are measured from 0.4 v to 2.4 v. 3. timing is guaranteed by design and characterization, and is not tested. 4. cycle-to-cycle jitter, and is guaranteed by design. the total input jitter (short term and long term combined) must be under 150 ps. 5. relock timing is guaranteed by design and characterization, and is not tested. pll-relock time is the maximum time required for pll lock after a stable vdd, ovdd, avdd, and sysclk are reached during the power-on reset sequence. this speci?ation also applies when the pll has been disabled and subsequently re-enabled during sleep mode. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll- relock time (100 m s) during the power-on reset sequence.
pid7v-603e hardware specifications 9 preliminary?ubject to change without notice figure 1 provides the sysclk input timing diagram. figure 1. sysclk input timing diagram 1.4.2.2 input ac speci?ations table 7 provides the input ac timing speci?ations for the pid7v-603e as de?ed in figure 2 and figure 3. table 7. input ac timing specifications 1 vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5% v dc, gnd = 0 v dc , 0 tj 105 c num characteristic 160, 166, 180, 200 mhz 220, 225, 233, 240 mhz unit notes min max min max 10a address/data/transfer attribute inputs valid to sysclk (input setup) 2.5 2.5 ns 2 10b all other inputs valid to sysclk (input setup) 4.0 3.5 ns 3 10c mode select inputs valid to hreset (input setup) (for dr tr y , qa ck and tlbisync ) 8?t sysclk 4, 5, 6, 7 11a sysclk to address/data/transfer attribute inputs invalid (input hold) 1.0 1.0 ns 2 vm cvil cvih sysclk 2 3 4 vm = midpoint voltage (1.4 v) 4 1 vm vm
10 pid7v-603e hardware specifications preliminary?ubject to change without notice figure 2 provides the input timing diagram for the pid7v-603e . figure 2. input timing diagram 11b sysclk to all other inputs invalid (input hold) 1.0 1.0 ns 3 11c hreset to mode select inputs invalid (input hold) (for dr tr y , qa ck , and tlbisync ) 0?ns4, 6, 7 note s: 1. input speci?ations are measured from the ttl level (0.8 or 2.0 v) of the signal in question to the 1.4 v of the rising edge of the input sysclk. input and output timings are measured at the pin. 2. address/data/transfer attribute input signals are composed of the following?[0?1], ap[0?], tt[0?], tc[0?], tbst , tsiz[0-2], gbl , dh[0?1], dl[0?1], dp[0?]. 3. all other input signals are composed of the following?s , abb , dbb , ar tr y , bg , aa ck , dbg , dbw o , t a , dr tr y , tea , dbdis , hreset , sreset , int , smi , mcp , tben, qa ck , tlbisync . 4. the setup and hold time is with respect to the rising edge of hreset (see figure 3). 5. t sysclk is the period of the external clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 6. these values are guaranteed by design, and are not tested. 7. this speci?ation is for con?uration mode only. also note that hreset must be held asserted for a minimum of 255 bus clocks after the pll-relock time during the power-on reset sequence. table 7. input ac timing specifications 1 (continued) vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5% v dc, gnd = 0 v dc , 0 tj 105 c num characteristic 160, 166, 180, 200 mhz 220, 225, 233, 240 mhz unit notes min max min max vm sysclk all inputs vm = midpoint voltage (1.4 v) 10a 10b 11a 11b
pid7v-603e hardware specifications 11 preliminary?ubject to change without notice figure 3 provides the mode select input timing diagram for the pid7v-603e. figure 3. mode select input timing diagram 1.4.2.3 output ac speci?ations table 8 provides the output ac timing speci?ations for the pid7v-603e as de?ed in figure 4. table 8. output ac timing specifications 1 vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5%, gnd = 0 v dc, 0 tj 105 c, c l = 50 pf (unless otherwise noted) num characteristic 160, 166, 180, 200 mhz 220, 225, 233, 240 mhz unit notes min max min max 12 sysclk to output driven (output enable time) 1.0 1.0 ns 13a sysclk to output valid (5.5 v to 0.8 v?s , abb , ar tr y , dbb ) 9.0 9.0 ns 3 13b sysclk to output valid (ts , abb , ar tr y , dbb ) 8.0 8.0 ns 5 14a sysclk to output valid (5.5 v to 0.8 v?ll except ts , abb , ar tr y , dbb ) 11.0 11.0 ns 3 14b sysclk to output valid (all except ts , abb , ar tr y , dbb ) 9.0 9.0 ns 5 15 sysclk to output invalid (output hold) 1.0 1.0 ns 2 16 sysclk to output high impedance (all except ar tr y , abb , dbb ) 8.5 8.0 ns 17 sysclk to abb , dbb , high impedance after precharge 1.0 1.0 t sysclk 4, 6 18 sysclk to ar tr y high impedance before precharge 8.0 7.5 ns mode pins hreset 10c 11c vm = midpoint voltage (1.4 v) vm
12 pid7v-603e hardware specifications preliminary?ubject to change without notice 19 sysclk to ar tr y precharge enable 0.2 * t sysclk + 1.0 0.2 * t sysclk + 1.0 ns 2, 4, 7 20 maximum delay to ar tr y precharge 1.0 1.0 t sysclk 4, 7 21 sysclk to ar tr y high impedance after precharge 2.0 2.0 t sysclk 5,7 notes : 1. all output speci?ations are measured from the 1.4 v of the rising edge of sysclk to the ttl level (0.8 v or 2.0 v) of the signal in question. both input and output timings are measured at the pin (see figure 4). 2. this minimum parameter assumes c l = 0 pf. 3. sysclk to output valid (5.5 v to 0.8 v) includes the extra delay associated with discharging the external voltage from 5.5 v to 0.8 v instead of from vdd to 0.8 v (5-v cmos levels instead of 3.3-v cmos levels). 4. t sysclk is the period of the external bus clock (sysclk) in nanoseconds (ns). the numbers given in the table must be multiplied by the period of sysclk to compute the actual time duration (in nanoseconds) of the parameter in question. 5. output signal transitions from gnd to 2.0 v or vdd to 0.8 v. 6. nominal precharge width for abb and dbb is 0.5 t sysclk . 7. nominal precharge width for ar tr y is 1.0 t sysclk . table 8. output ac timing specifications 1 (continued) vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5%, gnd = 0 v dc, 0 tj 105 c, c l = 50 pf (unless otherwise noted) num characteristic 160, 166, 180, 200 mhz 220, 225, 233, 240 mhz unit notes min max min max
pid7v-603e hardware specifications 13 preliminary?ubject to change without notice figure 4 provides the output timing diagram for the pid7v-603e. figure 4. output timing diagram sysclk 12 14 13 15 16 ts ar tr y abb , dbb vm vm vm = midpoint voltage (1.4 v) vm 13 20 18 17 21 19 15 16 all outputs (except ts , abb , dbb , artry )
14 pid7v-603e hardware specifications preliminary?ubject to change without notice 1.4.3 jtag ac timing speci?ations table 9 provides the jtag ac timing speci?ations as de?ed in figure 5, figure 6, figure 7 and figure 8. table 9. jtag ac timing specifications vdd = avdd = 2.5 5% v dc, ovdd = 3.3 5%, gnd = 0 v dc, 0 tj 105 c, c l = 50 pf num characteristic min max unit notes tck frequency of operation 0 16 mhz 1 tck cycle time 62.5 ns 2 tck clock pulse width measured at 1.4 v 25 ns 3 tck rise and fall times 0 3 ns 4 trst setup time to tck rising edge 13 ns 1 5 trst assert time 40 ns 6 boundary scan input data setup time 6 ns 2 7 boundary scan input data hold time 27 ns 2 8 tck to output data valid 4 25 ns 3 9 tck to output high impedance 3 24 ns 3 10 tms, tdi data setup time 0 ns 11 tms, tdi data hold time 25 ns 12 tck to tdo data valid 4 24 ns 13 tck to tdo high impedance 3 15 ns notes : 1. trst is an asynchronous signal. the setup time is for test purposes only. 2. non-test signal input timing with respect to tck. 3. non-test signal output timing with respect to tck.
pid7v-603e hardware specifications 15 preliminary?ubject to change without notice figure 5 provides the jtag clock input timing diagram. figure 5. jtag clock input timing diagram figure 6 provides the trst timing diagram . figure 6. trst timing diagram figure 7 provides the boundary-scan timing diagram. figure 7. boundary-scan timing diagram tck 2 2 1 vm vm vm 3 3 vm = midpoint voltage (1.4 v) 4 5 trst tck vm input data valid output data valid output data valid tck data inputs data outputs data outputs data outputs 6 7 8 8 9 vm vm
16 pid7v-603e hardware specifications preliminary?ubject to change without notice figure 8 provides the test access port timing diagram. figure 8. test access port timing diagram input data valid output data valid output data valid tck tdi, tms tdo tdo tdo 10 11 12 12 13 vm vm
pid7v-603e hardware specifications 17 preliminary?ubject to change without notice 1.5 powerpc 603e microprocessor pin assignments the following sections contain the pinout diagrams for the 603e. note that the 603e is offered in both ceramic quad ?t pack (cqfp) and ceramic ball grid array (bga) packages. 1.5.1 pinout diagram for the cqfp package figure 9 contains the cqfp pin assignments for the 603e. figure 9. pinout of the cqfp package gbl a1 a3 vdd a5 a7 a9 ognd gnd ovdd a11 a13 a15 vdd a17 a19 a21 ognd gnd ovdd a23 a25 a27 vdd dbw o dbg bg aa ck gnd a29 qreq ar tr y ognd vdd ovdd abb a31 dp0 gnd dp1 dp2 dp3 ognd vdd ovdd dp4 dp5 dp6 gnd dp7 dl23 dl24 ognd ovdd dl25 dl26 dl27 dl28 vdd ognd tt4 a0 a2 vdd a4 a6 a8 ovdd gnd ognd a10 a12 a14 vdd a16 a18 a20 ovdd gnd ognd a22 a24 a26 vdd dr tr y t a tea dbdis gnd a28 cse1 ts ovdd vdd ognd dbb a30 dl0 gnd dl1 dl2 dl3 ovdd vdd ognd dl4 dl5 dl6 gnd dl7 dl8 dl9 ovdd ognd dl10 dl11 dl12 dl13 vdd ovdd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 ovdd gnd ognd ci wt qa ck tben tlbisync rsr v ap0 ap1 ovdd ognd ap2 ap3 cse0 tc0 tc1 ovdd clk_out ognd br ape dpe c kstp_out ckstp _in hreset pll_cfg0 sysclk pll_cfg1 pll_cfg2 avdd pll_cfg3 vdd gnd lssd_mode l1_tstclk l2 _tstclk trst tck tms tdi tdo tsiz0 tsiz1 tsiz2 ovdd ognd tbst tt0 tt1 sreset int smi mcp tt2 tt3 ovdd gnd ognd 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 ovdd dl29 dl30 dl31 gnd dh31 dh30 dh29 ognd ovdd dh28 dh27 dh26 dh25 dh24 dh23 ognd dh22 ovdd dh21 dh20 dh19 dh18 dh17 dh16 ognd dh15 ovdd dh14 dh13 dh12 dh11 dh10 dh9 ognd ovdd dh8 dh7 dh6 dl22 dl21 dl20 ognd ovdd dl19 dl18 dl17 dh5 dh4 dh3 ognd ovdd dh2 dh1 dh0 gnd dl16 dl15 dl14 ognd 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 1 top view
18 pid7v-603e hardware specifications preliminary?ubject to change without notice 1.5.2 pinout diagram for the bga package figure 10 (in part a) shows the pinout of the bga package as viewed from the top surface. part b shows the side profile of the bga package to indicate the direction of the top surface view. part a figure 10. pinout of the bga package as viewed from the top surface a b c d e f g h j k l m n p r t 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 not to scale part b substrate assembly encapsulant view die
pid7v-603e hardware specifications 19 preliminary?ubject to change without notice 1.6 powerpc 603e microprocessor pinout listings the following sections provide the pinout listings for the 603e cqfp and bga packages. 1.6.1 pinout listing for the cqfp package table 10 provides the pinout listing for the 603e cqfp package. table 10. pinout listing for the 240-pin cqfp package signal name pin number active i/o a[0?1] 179, 2, 178, 3, 176, 5, 175, 6, 174, 7, 170, 11, 169, 12, 168, 13, 166, 15, 165, 16, 164, 17, 160, 21, 159, 22, 158, 23, 151, 30, 144, 37 high i/o aa ck 28 low input abb 36 low i/o ap[0?] 231, 230, 227, 226 high i/o ape 218 low output ar tr y 32 low i/o avdd 209 high input bg 27 low input br 219 low output ci 237 low output clk_out 221 output ckstp_in 215 low input ckstp_out 216 low output cse[0?] 1 225, 150 high output dbb 145 low i/o dbdis 153 low input dbg 26 low input dbw o 25 low input dh[0?1] 115, 114, 113, 110, 109, 108, 99, 98, 97, 94, 93, 92, 91, 90, 89, 87, 85, 84, 83, 82, 81, 80, 78, 76, 75, 74, 73, 72, 71, 68, 67, 66 high i/o dl[0?1] 143, 141, 140, 139, 135, 134, 133, 131, 130, 129, 126, 125, 124, 123, 119, 118, 117, 107, 106, 105, 102, 101, 100, 51, 52, 55, 56, 57, 58, 62, 63, 64 high i/o dp[0?] 38, 40, 41, 42, 46, 47, 48, 50 high i/o dpe 217 low output dr tr y 156 low input
20 pid7v-603e hardware specifications preliminary?ubject to change without notice gbl 1 low i/o gnd 9, 19, 29, 39, 49, 65, 116, 132, 142, 152, 162, 172, 182, 206, 239 low input hreset 214 low input int 188 low input lssd_mode 2 205 low input l1_tstclk 2 204 input l2_tstclk 2 203 input mcp 186 low input ognd 8, 18, 33, 43, 53, 60, 69, 77, 86, 95, 103, 111, 120, 127, 136, 146, 161, 171, 181, 193, 220, 228, 238 low input ovdd 3 10, 20, 35, 45, 54, 61, 70, 79, 88, 96, 104, 112, 121, 128, 138, 148, 163, 173, 183, 194, 222, 229, 240 high input pll_cfg[0?] 213, 211, 210, 208 high input qa ck 235 low input qreq 31 low output rsr v 232 low output smi 187 low input sreset 189 low input sysclk 212 input t a 155 low input tben 234 high input tbst 192 low i/o tc[0?] 224, 223 high output tck 201 input tdi 199 high input tdo 198 high output tea 154 low input tlbisync 233 low input tms 200 high input trst 202 low input table 10. pinout listing for the 240-pin cqfp package (continued) signal name pin number active i/o
pid7v-603e hardware specifications 21 preliminary?ubject to change without notice 1.6.2 pinout listing for the bga package table 11 provides the pinout listing for the 603e bga package. tsiz[0?] 197, 196, 195 high output ts 149 low i/o tt[0?] 191, 190, 185, 184, 180 high i/o vdd 3 4, 14, 24, 34, 44, 59, 122, 137, 147, 157, 167, 177, 207 high input wt 236 low output notes: 1. there are two cse signals in the 603e?se0 and cse1. the xa ts signal in the powerpc 603 microprocessor is replaced by the cse1 signal in both the pid6-603e and the pid7v-603e. 2. these are test signals for factory use only and must be pulled up to ovdd for normal machine operation. 3. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. table 11. pinout listing for the 255 bga package signal name pin number active i/o a[0?1] c16, e04, d13, f02, d14, g01, d15, e02, d16, d04, e13, go2, e15, h01, e16, h02, f13, j01, f14, j02, f15, h03, f16, f04, g13, k01, g15, k02, h16, m01, j15, p01 high i/o aa ck l02 low input abb k04 low i/o ap[0?] c01, b04, b03, b02 high i/o ape a04 low output ar tr y j04 low i/o avdd a10 bg l01 low input br b06 low output ci e01 low output ckstp_in d08 low input ckstp_out a06 low output clk_out d07 output cse[0?] b01, b05 high output dbb j14 low i/o dbg n01 low input dbdis h15 low input table 10. pinout listing for the 240-pin cqfp package (continued) signal name pin number active i/o
22 pid7v-603e hardware specifications preliminary?ubject to change without notice dbw o g04 low input dh[0?1] p14, t16, r15, t15, r13, r12, p11, n11, r11,t12, t11, r10, p09, n09, t10, r09, t09, p08, n08, r08, t08, n07, r07, t07, p06, n06, r06, t06, r05, n05, t05, t04 high i/o dl[0?1] k13, k15, k16, l16, l15, l13, l14, m16, m15, m13, n16, n15, n13, n14, p16, p15, r16, r14, t14, n10, p13, n12, t13, p03, n03, n04, r03, t01, t02, p04, t03, r04 high i/o dp[0?] m02, l03, n02, l04, r01, p02, m04, r02 high i/o dpe a05 low output dr tr y g16 low input gbl f01 low i/o gnd c05, c12, e03, e06, e08, e09, e11, e14, f05, f07, f10, f12, g06, g08, g09, g11, h05, h07, h10, h12, j05, j07, j10, j12, k06, k08, k09, k11, l05, l07, l10, l12, m03, m06, m08, m09, m11, m14, p05, p12 hreset a07 low input int b15 low input l1_tstclk 1 d11 input l2_tstclk 1 d12 input lssd_mode 1 b10 low input mcp c13 low input nc (no-connect) b07, b08, c03, c06, c08, d05, d06, h04, j16 ovdd c07, e05, e07, e10, e12, g03, g05, g12, g14, k03, k05, k12, k14, m05, m07, m10, m12, p07, p10 pll_cfg[0?] a08, b09, a09, d09 high input qa ck d03 low input qreq j03 low output rsrv d01 low output smi a16 low input sreset b14 low input sysclk c09 input t a h14 low input tben c02 high input tbst a14 low i/o tc[0?] a02, a03 high output table 11. pinout listing for the 255 bga package (continued) signal name pin number active i/o
pid7v-603e hardware specifications 23 preliminary?ubject to change without notice 1.7 powerpc 603e microprocessor package descriptions the following sections provide the package parameters and the mechanical dimensions for the 603e. note that the 603e is currently offered in two types of cqfp packages?he motorola wire-bond cqfp and the ibm c4-cqfp, as well as a common ceramic ball grid array (bga) package. 1.7.1 motorola wire-bond cqfp package description the following sections provide the package parameters and mechanical dimensions for the motorola wire- bond cqfp package. tck c11 input tdi a11 high input tdo a12 high output tea h13 low input tlbisync c04 low input tms b11 high input trst c10 low input ts j13 low i/o tsiz[0?] a13, d10, b12 high output tt[0?] b13, a15, b16, c14, c15 high i/o wt d02 low output vdd 2 f06, f08, f09, f11, g07, g10, h06, h08, h09, h11, j06, j08, j09, j11, k07, k10, l06, l08, l09, l11 voltdetgnd 3 f03 low output notes: 1. these are test signals for factory use only and must be pulled up to ovdd for normal machine operation. 2. ovdd inputs supply power to the i/o drivers and vdd inputs supply power to the processor core. 3. nc (no-connect) in the pid6-603e; internally tied to gnd in the pid7v-603e bga package to indicate to the power supply that a low-voltage processor is present. table 11. pinout listing for the 255 bga package (continued) signal name pin number active i/o
24 pid7v-603e hardware specifications preliminary?ubject to change without notice 1.7.1.1 package parameters the package parameters are as provided in the following list. the package type is 32 mm x 32 mm, 240-pin ceramic quad ?t pack. package outline 32 mm x 32 mm interconnects 240 pitch 0.5 mm (20 mil) 1.7.1.2 mechanical dimensions of the motorola wire-bond cqfp package figure 11 shows the mechanical dimensions for the wire-bond cqfp package. figure 11. mechanical dimensions of the motorola wire-bond cqfp package min. max. a 30.86 31.75 b 34.6 bsc c 3.75 4.15 d 0.5 bsc e 0.18 0.30 f 3.10 3.90 g 0.13 0.175 h 0.45 0.55 j 0.25 aa 1.80 ref ab 0.95 ref q 12 6 q 21 7 r 0.15 ref ? ab q i r r aa q 2 h pin 240 c a b pin 1 de *not to scale g f j die wire bonds ceramic body alloy 42 leads notes : 1. bsc?etween standard centers. 2. all measurements in mm. *reduced pin count shown for clarity. 60 pins per side
pid7v-603e hardware specifications 25 preliminary?ubject to change without notice 1.7.2 ibm c4-cqfp package description the following sections provide the package parameters and mechanical dimensions for the ibm c4-cqfp package. 1.7.2.1 package parameters the package parameters are as provided in the following list. the package type is 32 mm x 32 mm, 240-pin ceramic quad ?t pack. package outline 32 mm x 32 mm interconnects 240 pitch 0.5 mm lead plating material ni au lead plating thickness ni = 50 25 m -inch au = 13 5 m -inch solder joint sn/pb (10/90) lead encapsulation epoxy solder-bump encapsulation epoxy maximum module height 4.1 mm co-planarity speci?ation 0.08 mm note: no solvent can be used with the c4-cqfp package. see appendix a, ?eneral handling recommendations for the c4-cqfp package,?for details.
26 pid7v-603e hardware specifications preliminary?ubject to change without notice 1.7.2.2 mechanical dimensions of the ibm c4-cqfp package figure 12 shows the mechanical dimensions for the c4-cqfp package. figure 12. mechanical dimensions of the ibm solder-bump cqfp package *reduced pin count shown for clarity. 60 pins per side min max a 31.8 32.2 b 34.4 34.8 c 3.5 4.1 d 0.5 mm basic e 0.18 0.28 f 0.585 0.685 g 0.12 0.20 h 0.40 0.60 k 26.73 27.27 j min 0.35 ang 0.0 5.0 rad 0.25 clip leadframe chip tape cast ceramic epoxy dam solder-bump encapsulant h jmin radius 0.08 f g a b e c 0.13 total s a-b -c- 0.13 total s a-b 0.08 total m a-b d -a- pin 240 pin 1 * not to scale all measurements in mm ang -b- ceramic cap thermal grease k
pid7v-603e hardware specifications 27 preliminary?ubject to change without notice 1.7.3 bga package description the following sections provide the package parameters and mechanical dimensions for the motorola and ibm bga packages. 1.7.3.1 package parameters the package parameters are as provided in the following list. the package type is 21 mm x 21 mm, 255- lead ceramic ball grid array (bga). package outline 21 mm x 21 mm interconnects 255 pitch 1.27 mm (50 mil) package height minimum: 2.45 mm maximum: 3.00 mm ball diameter 0.89 mm (35 mil) maximum heat sink force 10 lbs
28 pid7v-603e hardware specifications preliminary?ubject to change without notice 1.7.3.2 mechanical dimensions of the bga package figure 13 provides the mechanical dimensions and bottom surface nomenclature of the motorola and ibm bga package. figure 13. mechanical dimensions and bottom surface nomenclature of the bga package notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 0.200 f t 255x a 2x a1 corner p n 0.200 2x ?e 12345678910111213141516 a b c d e f g h j k l m n p r t e 0.300 t 0.150 d c h 0.150 t b ?f k k g s s s s ?t dim millimeters inches min max min max a 21.000 bsc 0.827 bsc b 21.000 bsc 0.827 bsc c 2.450 3.000 0.097 0.118 d 0.820 0.930 0.032 0.036 g 1.270 bsc 0.050 bsc h 0.790 0.990 0.031 0.039 k 0.635 bsc 0.025 bsc n 5.000 16.000 0.197 0.630 p 5.000 16.000 0.197 0.630
pid7v-603e hardware specifications 29 preliminary?ubject to change without notice 1.8 system design information this section provides electrical and thermal design recommendations for successful application of the 603e. 1.8.1 pll con?uration the 603e pll is con?ured by the pll_cfg[0?] signals. for a given sysclk (bus) frequency, the pll con?uration signals set the internal cpu and vco frequency of operation. the pll con?uration for the pid7v-603e is shown in table 12 for nominal frequencies. table 12. powerpc pid7v-603e microprocessor pll configuration pll_cfg[0?] cpu frequency in mhz (vco frequency in mhz) bus-to- core multiplier core-to vco multiplier bus 25 mhz bus 33.33 mhz bus 40 mhz bus 50 mhz bus 60 mhz bus 66.67 mhz bus 75 mhz 0100 2x 2x 133 (266) 150 (300) 0101 2x 4x 0110 2.5x 2x 125 (250) 150 (300) 166 (333) 187 (375) 1000 3x 2x 120 (240) 150 (300) 180 (360) 200 (400) 225 (450) 1110 3.5x 2x 140 (280) 175 (350) 210 (420) 233 (466) 1010 4x 2x 133 (266) 160 (320) 200 (400) 240 (480) 0111 4.5x 2x 150 (300) 180 (360) 225 (450) 1011 5x 2x 125 (250) 166 (333) 200 (400) 1001 5.5x 2x 137 (275) 183 (366) 220 (440) 1101 6x 2x 150 (300) 200 (400) 240 (480) 0011 pll bypass 1111 clock off notes : 1. some pll con?urations may select bus, cpu, or vco frequencies which are not supported; see section 1.4.2.1, ?lock ac speci?ations, for valid sysclk and vco frequencies. 2. in pll-bypass mode, the sysclk input signal clocks the internal processor directly, the pll is disabled, and the bus mode is set for 1:1 mode operation. this mode is intended for factory use only. note : the ac timing speci?ations given in this document do not apply in pll-bypass mode. 3. in clock-off mode, no clocking occurs inside the 603e regardless of the sysclk input.
30 pid7v-603e hardware specifications preliminary?ubject to change without notice 1.8.2 pll power supply filtering the avdd power signal is provided on the 603e to provide power to the clock generation phase-locked loop. to ensure stability of the internal clock, the power supplied to the avdd input signal should be ?tered using a circuit similar to the one shown in figure 14. the circuit should be placed as close as possible to the avdd pin to ensure it ?ters out as much noise as possible. the 0.1 m f capacitor should be closest to the avdd pin, followed by the 10 m f capacitor, and ?ally the 10 w resistor to vdd. these traces should be kept short and direct. figure 14. pll power supply filter circuit 1.8.3 decoupling recommendations due to the 603es dynamic power management feature, large address and data buses, and high operating frequencies, the 603e can generate transient power surges and high frequency noise in its power supply, especially while driving large capacitive loads. this noise must be prevented from reaching other components in the 603e system, and the 603e itself requires a clean, tightly regulated source of power. therefore, it is recommended that the system designer place at least one decoupling capacitor at each vdd and ovdd pin of the 603e. it is also recommended that these decoupling capacitors receive their power from separate vdd, ovdd, and gnd power planes in the pcb, utilizing short traces to minimize inductance. these capacitors should vary in value from 220 pf to 10 m f to provide both high- and low-frequency ?tering, and should be placed as close as possible to their associated vdd or ovdd pin. suggested values for the vdd pins?20 pf (ceramic), 0.01 m f (ceramic), and 0.1 m f (ceramic). suggested values for the ovdd pins?.01 m f (ceramic), 0.1 m f (ceramic), and 10 m f (tantalum). only smt (surface mount technology) capacitors should be used to minimize lead inductance. in addition, it is recommended that there be several bulk storage capacitors distributed around the pcb, feeding the vdd and ovdd planes, to enable quick recharging of the smaller chip capacitors. these bulk capacitors should also have a low esr (equivalent series resistance) rating to ensure the quick response time necessary. they should also be connected to the power and ground planes through two vias to minimize inductance. suggested bulk capacitors?00 m f (avx tps tantalum) or 330 m f (avx tps tantalum). 1.8.4 connection recommendations to ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. unused active low inputs should be tied to vdd. unused active high inputs should be connected to gnd. all nc (no-connect) signals must remain unconnected. power and ground connections must be made to all external vdd, ovdd, and gnd pins of the 603e. 1.8.5 pull-up resistor requirements the 603e requires high-resistive (weak: 10 k w ) pull-up resistors on several control signals of the bus interface to maintain the control signals in the negated state after they have been actively negated and released by the 603e or other bus master. these signals are?s , abb , dbb , and ar tr y . vdd avdd 10 w 10 m f 0 . 1 m f gnd
pid7v-603e hardware specifications 31 preliminary?ubject to change without notice in addition, the 603e has three open-drain style outputs that require pull-up resistors (weak or stronger: 4.7 k w ?0 k w ) if they are used by the system. these signals are?pe , dpe , and ckstp_out . during inactive periods on the bus, the address and transfer attributes on the bus are not driven by any master and may ?at in the high-impedance state for relatively long periods of time. since the 603e must continually monitor these signals for snooping, this ?at condition may cause excessive power draw by the input receivers on the 603e. it is recommended that these signals be pulled up through weak (10 k w ) pull- up resistors or restored in some manner by the system. the snooped address and transfer attribute inputs are?[0?1], ap[0?], tt[0?], tbst , and gbl . the data bus input receivers are normally turned off when no read operation is in progress and do not require pull-up resistors on the data bus. 1.8.6 thermal management information this section provides thermal management data for the 603e; the information found in the ?st sub-sections (section 1.8.6.1.1, ?hermal characteristics,?through section 1.8.6.2.2, ?hermal management example? is based on a typical desktop con?uration using a 240 lead, 32 mm x 32 mm, motorola wire-bond cqfp package and an ibm c4-cqfp package. the heat sink used for this data is a pin? con?uration from thermalloy, part number 2338. the ibm c4-cqfp also uses a ?t aluminum plate with dimensions of 24 x 24 mm and 1.5 mm thickness. the data found in the subsequent sub-sections concerns 603es packaged in the 255-lead 21 mm multi-layer ceramic (mlc), ceramic bga package. data is shown for two cases, the exposed-die case (no heat sink) and using the thermalloy 2338-pin ? heat sink. 1.8.6.1 motorola wire-bond cqfp package this section provides thermal management data for the 603e; this information is based on a typical desktop con?uration using a 240 lead, 32 mm x 32 mm, motorola wire-bond cqfp package. the heat sink used for this data is a pin? con?uration from thermalloy, part number 2338. 1.8.6.1.1 thermal characteristics the thermal characteristics for a wire-bond cqfp package are as follows: thermal resistance (junction-to-case) = r q jc or q jc = 2.2 c/watt (junction-to-case) 1.8.6.1.2 thermal management example the following example is based on a typical desktop con?uration using a motorola wire-bond cqfp package. the heat sink used for this data is a pin? heat sink #2338 attached to the wire-bond cqfp package with thermal grease. figure 15 provides a thermal management example for the motorola cqfp package.
32 pid7v-603e hardware specifications preliminary?ubject to change without notice figure 15. motorola cqfp thermal management example the junction temperature can be calculated from the junction-to-ambient thermal resistance, as follows: junction temperature: t j = t a + r q ja * p or t j = t a + (r q jc + r cs + r sa ) * p where : t a is the ambient temperature in the vicinity of the device r q ja is the junction-to-ambient thermal resistance r q j c is the junction-to-case thermal resistance of the device r cs is the case-to-heat sink thermal resistance of the interface material r sa is the heat sink-to-ambient thermal resistance p is the power dissipated by the device in this environment, it can be assumed that all the heat is dissipated to the ambient through the heat sink, so the junction-to-ambient thermal resistance is the sum of the resistances from the junction to the case, from the case to the heat sink, and from the heat sink to the ambient. note that veri?ation of external thermal resistance and case temperature should be performed for each application. thermal resistance can vary considerably due to many factors including degree of air turbulence. for a power dissipation of 2.5 watts in an ambient temperature of 40 c at 1 m/sec with the heat sink measured above, the junction temperature of the device would be as follows: t j = t a + r q ja * p t j = 40 c + (10 c/watt * 2.5 watts) = 65 c which is well within the reliability limits of the device. 0123 5 0 5 10 15 20 25 30 35 motorola wire-bond cqfp with heat sink forced convection (m/sec) junction-to-ambient thermal resistance ( c/watt) 4
pid7v-603e hardware specifications 33 preliminary?ubject to change without notice notes : 1. junction-to-ambient thermal resistance is based on measurements on single-sided printed circuit boards per semi (semiconductor equipment and materials international) g38-87 in natural convection. 2. junction-to-case thermal resistance is based on measurements using a cold plate per semi g30-88 with the exception that the cold plate temperature is used for the case temperature. the vendors who supply heat sinks are aavid engineering, ierc, thermalloy, and wake?ld engineering. contact information for these vendors follows: thermalloy 214-243-4321 2021 w. valley view lane p.o. box 810839 dallas, tx 75731 international electronic research corporation (ierc) 818-842-7277 135 w. magnolia blvd. burbank, ca 91502 aavid engineering 603-528-3400 one kool path laconic, nh 03247-0440 wake?ld engineering 617-245-5900 60 audubon rd. wake?ld, ma 01880 any of these vendors can supply heat sinks with suf?ient thermal performance. 1.8.6.2 ibm c4-cqfp package this section provides thermal management data for the 603e; this information is based on a typical desktop con?uration using a 240 lead, 32 mm x 32 mm, ibm c4-cqfp package. the heat sink used for this data is a pin? con?uration from thermalloy, part number 2338 and a ?t aluminum plate with dimensions of 24 x 24 mm and 1.5 mm thickness. 1.8.6.2.1 thermal characteristics the thermal characteristics for a c4-cqfp package are as follows: thermal resistance (junction-to-heat sink) = r q js or q js = 0.03 c/watt (junction-to-heat sink) 1.8.6.2.2 thermal management example the following example is based on a typical desktop con?uration using an ibm c4-cqfp package. the heat sink used for this data is a pin? heat sink #2338 attached to the c4-cqfp package with 2-stage epoxy. the junction temperature can be calculated from the junction-to-ambient thermal resistance, as follows: junction temperature: t j = t a + r q ja * p or t j = t a + (r q j s + r sa ) * p
34 pid7v-603e hardware specifications preliminary?ubject to change without notice where : t a is the ambient temperature in the vicinity of the device r q ja is the junction-to-ambient thermal resistance r q j s is the junction-to-heat sink thermal resistance (includes thermal grease or thermal adhesive) r sa is the heat sink-to-ambient thermal resistance p is the power dissipated by the device note : r q js includes the resistance of a typical layer of thermal compound. if a lower conductivity material is used, its thermal resistance must be included. in this environment, it can be assumed that all the heat is dissipated to the ambient through the heat sink, so the junction-to-ambient thermal resistance is the sum of the resistances from the junction to the heat sink and from the heat sink to the ambient. note that veri?ation of external thermal resistance and case temperature should be performed for each application. thermal resistance can vary considerably due to many factors including degree of air turbulence. figure 16 provides a thermal management example for the ibm c4-cqfp package. figure 16. ibm c4-cqfp thermal management example for a power dissipation of 2.5 watts in an ambient temperature of 40 c at 1 m/sec with the pin? heat sink measured above, the junction temperature of the device is as follows: t j = t a + r q ja * p t j = 40 c + (9.1 c/watt * 2.5 watts) = 63 c which is well within the reliability limits of the device. forced convection (m/sec) 0 5 10 15 20 25 30 35 40 0 0.25 0.5 1 2 exposed die aluminum plate pinfin junction-to-ambient thermal resistance (?/w) ibm c4-cqfp
pid7v-603e hardware specifications 35 preliminary?ubject to change without notice notes : 1. junction-to-ambient thermal resistance is based on modeling. 2. junction-to-heat sink thermal resistance is based on measurements and model using thermal test chip and thermal couple which is placed on the base of the heat sink. 3. q ja is not measured for 0.25 m/sec convection for the pin?. the vendors who supply heat sinks are aavid engineering, thermalloy, and wake?ld engineering. any of these vendors can supply heat sinks with suf?ient thermal performance. refer to section 1.8.6.1.2, ?hermal management example,?for contact information. 1.8.6.3 motorola and ibm cbga package the data found in this section concerns 603es packaged in the 255-lead 21 mm multi-layer ceramic (mlc), ceramic bga package. data is shown for two cases, the exposed-die case (no heat sink) and using the thermalloy 2338-pin ? heat sink. 1.8.6.3.1 thermal characteristics the internal thermal resistance for this package is negligible due to the exposed die design. a heat sink is attached directly to the silicon die surface only when external thermal enhancement is necessary. additionally, the cbga package offers an exceptional thermal connection to the card and power planes. heat generated at the chip is dissipated through the package, the heat sink (when used) and the card. the parallel heat ?w paths result in the lowest overall thermal resistance as well as offer signi?antly better power dissipation capability when a heat sink is not used. 1.8.6.3.2 thermal management example the following example is based on a typical desktop con?uration using a solder-bump 21 mm cbga package. the heat sink shown is the thermalloy pin? heat sink #2338 attached directly to the exposed die with a two-stage thermally conductive epoxy. the calculations are performed exactly as shown in the previous section. figure 17 shows typical thermal performance data for the 21 mm cbga package mounted to a test card.
36 pid7v-603e hardware specifications preliminary?ubject to change without notice figure 17. cbga thermal management example temperature calculations are also performed identically to those in the previous section. for a power dissipation of 2.5 watts in an ambient of 40 c at 1.0 m/sec, the associated overall thermal resistance and junction temperature, found in table 13, will result. vendors such as aavid engineering inc., thermalloy, and wake?ld engineering can supply heat sinks with a wide range of thermal performance. refer to section 1.8.6.1.2, ?hermal management example,?for contact information. table 13. thermal resistance and junction temperature con?uration q ja ( c/w) tj ( c) exposed die (no heat sink) 18.4 86 with 2338 heat sink 5.3 53 approach air velocity (m/sec) 0 5 10 15 20 01234 q ja (?/w) ibm cbga with exposed die 25 5 ibm cbga with thermalloy 2338b-pin fin heat sink assumptions: 1. 2p card with 1 oz cu planes 2. 63 mm x 76 mm card 3. air flow on both sides of card 4. vertical orientation 5. 2-stage epoxy heat sink attach
pid7v-603e hardware specifications 37 preliminary?ubject to change without notice 1.9 ordering information this section provides the part numbering nomenclature for the pid7v-603e. note that the individual part numbers correspond to a maximum processor core frequency. for available frequencies, contact your local motorola or ibm sales of?e. 1.9.1 motorola part number key figure 18 provides the motorola part numbering nomenclature for the pid7v-603e. in addition to the processor frequency, the part numbering scheme also consists of a part modi?r and application modi?r. the part modi?r indicates any enhancement(s) in the part from the original production design. the bus divider may specify special bus frequencies or application conditions. each part number also contains a revision code. this refers to the die mask revision number and is speci?d in the part numbering scheme for identi?ation purposes only. figure 18. motorola part number key 1.9.2 ibm part number key figure 19 provides a description of the ibm part number for the pid7v-603e. figure 19. ibm part number key mpc 603 p xx xxx x x product code part identifier part modifier application modifier (p = enhanced, low-voltage) (fe = wire-bond cqfp (l = any valid pll configuration ) package rx = cbga w/o lid) processor frequency (contact motorola sales office) revision level ibm25ppc 603 ev? x?xx? bus divider product code (contact ibm sales office) part identifier (e = enhanced, v = low-voltage) package (f = c4-cqfp, b = cbga) part modifier processor frequency revision level (contact ibm sales office)
38 pid7v-603e hardware specifications preliminary?ubject to change without notice appendix a general handling recommendations for the c4-cqfp package the following list provides a few guidelines for package handling: handle the electrostatic discharge sensitive (esd) package with care before, during, and after processing. do not apply any load to exceed 3 kg after assembly. components should not be hot-dip tinned. the package encapsulation is an acrylated urethane. use adequate ventilation (local exhaust) for all elevated temperature processes. the package parameters are as follows: heat sink adhesive aieg-7655 ibm reference drawing 99f4869 test socket yamaichi qfp-po 0.5-240p signal 165 power/ground 75 total 240 a.1 package environmental, operation, shipment, and storage requirements the environmental, operation, shipment, and storage requirements are as follows: make sure that the package is suitable for continuous operation under business of?e environments. operating environment: 10 c to 40 c, 8% to 80% relative humidity storage environment: 1 c to 60 c, up to 80% relative humidity shipping environment: 40 c to 60 c, 5% to 100% relative humidity this component is quali?d to meet jedec moisture class 2. after expiration of shelf life, packages may be baked at 120 c (+10/? c) for 4 hours minimum and then be used or repackaged. shelf life is as speci?d by jedec for moisture class 2 components. a.2 card assembly recommendations this section provides recommendations for card assembly process. follow these guidelines for card assembly. this component is supported for aqueous, ir, convection re?w, and vapor phase card assembly processes. the temperature of packages should not exceed 220 c for longer than 5 minutes. the package entering a cleaning cycle must not be exposed to temperature greater than that occurring during solder re?w or hot air exposure. it is not recommended to re-attach a package that is removed after card assembly.
pid7v-603e hardware specifications 39 preliminary?ubject to change without notice during the card assembly process, no solvent can be used with the c4fp, and no more than 3 kg of force must be applied normal to the top of the package prior to, during, or after card assembly. other details of the card assembly process follow: solder paste either water soluble (for example, alpha 1208) or no clean solder stencil thickness 0.152 mm solder stencil aperature width reduced to 0.03 mm from the board pad width placement tool panasonic mpa3 or equivalent solder re?w infrared, convection, or vapor phase solder re?w pro?e infrared and/or convection average ramp-up?.48 to 1.8 c/second time above 183 c?5 to 145 seconds minimum lead temperature?00 c maximum lead temperature?40 c maximum c4fp temperature?45 c vapor phase preheat (board)?0 c to 150 c time above 183 c?0 to 145 seconds minimum lead temperature?00 c maximum c4fp temperature?20 c egress temperature?elow 150 c clean after re?w de-ionized (d.i.) water if water-soluble paste is used cleaner requirements?onveyorized, in-line minimum of four washing chambers ?pre-clean chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 70 c minimum, dwell time of 24 seconds minimum, water is not re-used, water ?w rate of 30 liters/minute. ?wash chamber #1: top and bottom sprays, minimum top-side pressure of 48 psig, minimum bottom-side pressure of 44 psig, water temperature of 62.5 c ( 2.5 c), dwell time of 48 seconds minimum, water ?w rate of 350 liters/minute. ?wash chamber #2: top and bottom sprays, minimum top-side pressure of 32 psig, minimum bottom-side pressure of 28 psig, water temperature of 72.5 c ( 2.5 c), dwell time of 48 seconds minimum, water ?w rate of 325 liters/minute. ?final rinse chamber: top and bottom sprays, minimum top-side pressure of 25 psig, water temperature of 72.5 c minimum, dwell time of 24 seconds minimum, water ?w rate of 30 liters/minute. no cleaning required if ?o clean solder paste?is used touch-up and repair water soluble (for example, kester 450) or no clean flux c4fp removal hot air rework c4fp replace hand solder
information in this document is provided solely to enable system and software implementers to use powerpc microprocessors. there are no express or implied copyright or patent licenses granted hereunder by motorola or ibm to design, modify the design of, or fabricate circuits based on the information in this document. the powerpc 603e microprocessor embodies the intellectual property of motorola and of ibm. however, neither motorola nor ibm assumes any responsibility or liability as to any aspects of the performance, operation, or other attributes of the microprocessor as marketed by the other party or by any third party. neither motorola nor ibm is to be considered an agent or representative of the other, and neither has assumed, created, or granted hereby any right or authority to the other, or to any third party, to assume or create any express or implied obligations on its behalf. information such as errata sheets and data sheets, as well as sales terms and conditions such as prices, schedules, and support, for the product may vary as between parties selling the product. accordingly, customers wishing to learn more information about the products as marketed by a given party should contact that party. both motorola and ibm reserve the right to modify this document and/or any of the products as described herein without further notice. nothing in this document, nor in any of the errata sheets, data sheets, and other supporting documentation, shall be interpreted as the conveyance by motorola or ibm of an express warranty of any kind or implied warranty, representation, or guarantee regarding the merchantability or fitness of the products for any particular purpose . neither motorola nor ibm assumes any liability or obligation for damages of any kind arising out of the application or use of these materials. any warranty or other obligations as to the products described herein shall be undertaken solely by the marketing party to the customer, under a separate sale agreement between the marketing party and the customer. in the absence of such an agreement, no liability is assumed by motorola, ibm, or the marketing party for any damages, actual or otherwise. ?ypical parameters can and do vary in different applications. all operating parameters, including ?ypicals, must be validated for each customer application by customers technical experts. neither motorola nor ibm convey any license under their respective intellectual property rights nor the rights of others. neither motorola nor ibm makes any claim, warranty, or representation, express or implied, that the products described in this document are designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the product could create a situation where personal injury or death may occur. should customer purchase or use the products for any such unintended or unauthorized application, customer shall indemnify and hold motorola and ibm and their respective of?ers, employees, subsidiaries, af?iates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorneys fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that motorola or ibm was negligent regarding the design or manufacture of the part. motorola and are registered trademarks of motorola, inc. motorola, inc. is an equal opportunity/af?mative action employer. ibm, the ibm logo, and ibm microelectronics are trademarks of international business machines corporation. the powerpc name, the powerpc logotype, powerpc 603, and powerpc 603e are trademarks of international business machines corporation, used by motorola under license from international business machines corporation. international business machines corporation is an equal opportunity/af?mative action employer. international business machines corporation: ibm microelectronics division, 1580 route 52, bldg. 504, hopewell junction, ny 12533-6531; tel. (800) powerpc world wide web address : http://www.chips.ibm.com/products/ppc http://www.ibm.com motorola literature distribution centers : usa/europe: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036; tel.: 1-800-441-2447 japan : nippon motorola ltd.; tatsumi-spd-jldc, toshikatsu otsuki, 6f seibu- butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan; tel.: 03-3521-8315 hong kong : motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong; tel.: 852-26629298 technical information : motorola inc. sps customer support center; (800) 521-6274. document comments : fax (512) 891-2638, attn: risc applications engineering.

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